1. Field of the Invention
The present invention relates to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2009-225298, filed Sep. 29, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
The high integration of recent semiconductor devices has been achieved by miniaturization of transistors. The miniaturization of transistors has been reaching its limit If the size of transistors is further reduced, the transistors might malfunction due to the short channel effect.
To solve the problem, there has been provided a method of forming three-dimensional transistors including a silicon pillar vertically extending from a main surface of a semiconductor board. Such a three-dimensional transistor has a smaller occupied area and a fully-depleted SOI structure, and thereby can achieve a larger drain current and 4F2 DRAM cells.
When a vertical transistor including a silicon pillar is used as a cell transistor of a semiconductor memory device, generally, one of impurity diffusion regions, which is a source or a drain, is connected to a bit line. The other impurity diffusion region is connected to a memory element (cell capacitor in the case of DRAM). Generally, a memory element, such as a cell capacitor, is positioned above a cell transistor. Therefore, the memory element is disposed above the silicon pillar, and the bit line is disposed below the silicon pillar.
However, the semiconductor board is disposed below the silicon pillar. For this reason, it is necessary to embed a bit line in the semiconductor board. Regarding structures of bit lines, Japanese Patent Laid-Open Publication No. 2004-303966 discloses a method of forming a silicide layer over a bit line contact, and forming a metal wiring contact and a metal wiring over the silicide layer. However, the semiconductor device disclosed in the above related art does not include a pillar-type transistor.
Japanese Patent Laid-Open Publication No. 2007-5699 discloses a semiconductor device in which a diffusion layer, which is a bit line, is formed in a semiconductor board. However, the diffusion layer has high specific electrical resistance, thereby decreasing the operating speed of the semiconductor device.
Japanese Patent Laid-Open Publication No. 2009-10366 discloses a semiconductor device in which an embedded bit line is formed below a pillar portion. The bit line has a low resistance region made of a metal and the like, and a silicon region made of a silicon material. However, when a metal is used as the embedded bit line, a silicide layer might be formed, in a following thermal treatment process, between the metal forming the bit line and the silicon forming the semiconductor board. It is difficult to control the growth of the silicide layer. For this reason, if a silicide layer is excessively grown, the transistor might malfunction.